1. Field of the Invention
The present invention relates to a flip chip interface circuit of a semiconductor memory device and a method thereof. More particularly, the present invention relates to a circuit and a method for determining an interface with bonding option data when two chips of a semiconductor memory device are combined in a mirror type arrangement and packaged into a flip chip.
2. Description of the Related Art
Generally, a semiconductor package is made by forming signal input/output terminals in a main board and mounting semiconductor chip packages thereto, such that single devices and integrated circuits, etc., that are formed by depositing various electronic circuits and wires on a substrate may be protected from various external environments such as dust, moisture, electrical and mechanical loads, and such that the performance of the semiconductor chip may be optimized. As semiconductor chips become more highly integrated, having higher performance, higher functions, and a higher degree of miniaturization, semiconductor packages accordingly require multiple pins and greater miniaturization techniques to reduce the size and weight of the packages. Accordingly, a ball grid array (BGA) package that uses solder balls as input/output terminals has been developed. However, because bonding wires are used for connecting the semiconductor chips to the package, and because the size of the package is increased due to loops in the bonding wires, the density of the package and the design margin of electrical patterns on a circuit board, such as a motherboard, are limited.
To eliminate the wire bonding loops, a flip chip technique has been developed. A typical flip chip is a semiconductor chip in which a bump made of a soft metal, such as solder, gold (Au), lead (Pb), or silver (Ag), is formed on each input/output pad on the surface of the semiconductor chip. The chip is mounted by bonding the chip with the bumps facedown on a printed circuit board or a main board without using wires. In the sense that the semiconductor chip is turned over when bonded on a circuit board, it is called a flip chip.
A flip chip bonding technique requires forming a bump on an integrated circuit of a semiconductor chip and connecting the chip to a substrate by using the bump. In the flip chip bonding technique, the bump may be simultaneously connected to the integrated circuit when providing the substrate with the semiconductor chip, and the electrical paths formed therein are short. Therefore, a flip chip bonding technique is frequently used in manufacturing electronic products requiring a light weight, a high degree of miniaturization, and a high level of density, and is frequently applied to fabrication of semiconductor chip packages such as ball grid array (BGA) packages and chip scale packages (or chip size packages).
FIG. 1 illustrates a cross sectional view of a flip chip package in which two identical chips are bonded facedown. The flip chip package includes a first semiconductor chip 10, a second semiconductor chip 12 that is identical to the first semiconductor chip 10, and an assembling lead frame 14 that is provided between the first and second semiconductor chips 10 and 12, respectively. The first and second semiconductor chips 10 and 12 each have first to sixth pads #1, #2, #3, #4, #5, #6. The lead frame 14 has first to sixth landing pads P1, P2, P3, P4, P5, P6, which correspond to and are aligned with the first to sixth pads #1, #2, #3, #4, #5, #6 of the first and second semiconductor chips 10 and 12, respectively. The first to sixth pads #1, #2, #3, #4, #5, #6 of the first semiconductor chip 10 and the sixth to first pads #6, #5, #4, #3, #2, #1 of the second semiconductor chip 12 are in a mirror type connection to the first to sixth landing pads P1, P2, P3, P4, P5, P6. The first semiconductor chip 10 will be referred to as the TOP chip and the second semiconductor chip 12 as the BOT chip for the following discussion of FIG. 2, which illustrates a perspective view of the flip chip pad illustrates in FIG. 1.
Referring to FIG. 2, the first to sixth pads of the second semiconductor chip 12 that are positioned below the assembling lead frame 14 are arranged in the order of #1, #2, #3, #4, #5, #6 from right to left. The first to sixth pads of the first semiconductor chip 10 that are placed above the assembling lead frame 14 are arranged in the order of #1, #2, #3, #4, #5, #6 from left to right. Thus, the pads of the first semiconductor chip 10 and the second semiconductor chip 12 are connected to one another through the landing pads P1, P2, P3, P4, P5, P6. That is, the first landing pad P1 is connected between the first pad #1 of the first semiconductor chip 10 and the sixth pad #6 of the second semiconductor chip 12, the second landing pad P2 is connected between the second pad #2 of the first semiconductor chip 10 and the fifth pad #5 of the second semiconductor chip 12, etc.
When two identical chips are assembled as described above, information about a chip to be arranged on top of an assembling lead frame and a chip to be arranged on a bottom of the assembling lead frame should be given to a chip and the interface should be controlled accordingly. Thus, techniques for preventing interface conflicts are required.